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1 ? fn8214.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. X96010 sensor conditioner wi th dual look up table memory and dacs features ? two programmable current generators ?3.2 ma max. ?8-bit (256 step) resolution ?external resistor pins to set full scale cur- rent output ? external sensor input (single ended) ? integrated 8-bit a/d converter ? internal voltage reference with output/input ? temperature compensation ? eeprom look-up tables ? hot pluggable ? write protection circuitry ?intersil blocklock? ?logic controlled protection ? 2-wire bus with 3 slave address bits ? 3v to 5.5v, single supply operation ? package ?14 ld tssop ? pb-free plus anneal available (rohs compliant) applications ? pin diode bias control ? rf pa bias control ? temperature compensated process control ? laser diode bias control ?fan control ? motor control ? sensor signal conditioning ? data aquisiti on applications ? gain vs. temperature control ? high power audio ? open loop temperature compensation ? close loop current, voltage, pressure, temper- ature, speed, position programmable voltage sources, electronic loads, output amplifiers, or function generator description the X96010 is a highly integrated bias controller which incorporates two digitally controlled programmable cur- rent generators and temperature compensation with dedicated look-up tables. all functions of the device are controlled via a 2-wire digital serial interface. two temperature compensated programmable cur- rent generators, vary the output current with tempera- ture according to the contents of the associated nonvolatile look-up table. the look-up table may be programmed with arbitrary data by the user via the 2- wire serial port, and an external temperature sensor may be used to control the output current response. pin configuration ordering information part number part marking temp range (c) package X96010v14i X96010v i -40 to 100 14 ld tssop X96010v14iz (note) X96010vi z -40 to 100 14 ld tssop (pb-free) note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. vss a2 3 4 i2 r1 r2 vcc a0 1 10 11 9 12 7 8 scl 6 a1 2 wp 5 vref vsense 13 14 i1 sda tssop 14l data sheet october 25, 2005
2 fn8214.1 october 25, 2005 block diagram pin assignments sda scl wp 2-wire i2 vref r2 vsense interface a2, a1, a0 dac 2 adc look-up table 1 look-up table 2 control & status mux mux i1 r1 dac 1 mux mux voltage reference tssop pin pin name pin description 1a0 device address select pin 0. this pin determines the lsb of the device address required to com- municate using the 2-wire interface. the a0 pin has an on-chip pull-down resistor. 2a1 device address select pin 1. this pin determines the intermediate bit of the device address re- quired to communicate using the 2-wire interface. the a1 pin has an on-chip pull-down resistor. 3a2 device address select pin 2. this pin determines the msb of the device address required to com- municate using the 2-wire interface. the a2 pin has an on-chip pull-down resistor. 4vcc supply voltage. 5wp write protect control pin. this pin is a cmos compatible input. when low, write protection is enabled preventing any ?write? operation. when high, various areas of the memory can be protect- ed using the block lock bits bl1 and bl0. the wp pin has an on-chip pull-down resistor, which en- ables the write protection when this pin is left floating. 6scl serial clock. this is a ttl compatible input pin. this input is the 2-wire interface clock contro lling data input and output at the sda pin. 7sda serial data. this pin is the 2-wire interface data into or out of the device. it is ttl compatible when used as an input, and it is open drain when used as an output. this pin requires an external pull up resistor. 8i1 current generator 1 output. this pin sinks or sources current. the magnitude and direction of the current is fully programmable and adaptive. the resolution is 8 bits. 9r1 current programming resistor 1. a resistor between this pin and vss can set the maximum output current available at pin i1. if no resistor is used, the maximum current must be selected using control register bits. 10 r2 current programming resistor 2. a resistor between this pin and vss can set the maximum output current available at pin i2. if no resistor is used, the maximum current must be selected using control register bits. 11 vss ground. 12 vsense sensor voltage input. this voltage input may be used to drive the input of the on-chip a/d converter. 13 vref reference voltage input or output. this pin can be configured as either an input or an output. as an input, the voltage at this pin is provided by an external source. as an output, the voltage at this pin is a buffered output voltage of the on-chip bandgap reference circuit. in both cases, the voltage at this pin is the reference for the a/d converter and the two d/a converters. 14 i2 current generator 2 output. this pin sinks or sources current. the magnitude and direction of the current is fully programmable and adaptive. the resolution is 8 bits. X96010
3 fn8214.1 october 25, 2005 absolute maximum ratings all voltages are referred to vss. temperature under bias ................... -65c to +100c storage temperature ......... ............... -65c to +150c voltage on every pin except vcc ................ -1.0v to +7v voltage on vcc pin .............................................0 to 5.5v d.c. output current at pin sda ...................... 0 to 5 ma d.c. output current at pins r1, r2, and vref ........................................................ -0.50 to 1 ma d.c. output current at pins i1 and i2 ....... -3.5 to +3.5ma lead temperature (soldering, 10s) .................... 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating con- ditions for extended periods ma y affect device reliability. recommended operating conditions parameter min. max. units temperature -40 +100 c temperature while writing to memory 0 +70 c voltage on vcc pin 35.5v voltage on any other pin -0.3 vcc + 0.3 v electrical characteristics (conditions are as follows , unless otherwise specified) all typical values are for 25c ambient temperature and 5v at pin vcc. maximum and minimu m specifications are over the recommended operating conditions. all voltages are referred to the voltage at pin vss. bit 3 in control register 0 is ?1?, while all other bits in control registers are ?0?. 255 ? , 0.1%, resistor connected between r1 and vss, and another between r2 and vss. 400khz ttl input at sc l. sda pulled to vcc through an external 2k ? resistor. 2-wire interface in ?standby? (see notes 1 and 2 on page 5). wp , a0, a1, and a2 floating. vref pin unloaded. symbol parameter min typ max unit test conditions / notes iccstby standby current into vcc pin 2 ma r1 and r2 floating, vref unloaded. iccfull full operation current into vcc pin 15 ma 2-wire interface reading from memory, i 1 and i 2 both connected to vss, dac input bytes: ffh, vref unloaded. iccwrite nonvolatile write current into vcc pin 4 ma average from start condition until t wp after the stop condition wp : vcc, r1 and r2 floating, vref unloaded. i pldn on-chip pull down current at wp , a0, a1, and a2 0120 av(wp ), v(a0), v(a1), and v(a2) from 0v to vcc v ilttl scl and sda, input low voltage 0.8 v v ihttl scl and sda, input high voltage 2.0 v i inttl scl and sda input current -1 10 a pin voltage between 0 and vcc, and sda as an input. v olsda sda output low voltage 0 0.4 v i(sda) = 2 ma i ohsda sda output high current 0 100 a v(sda) = vcc v ilcmos wp , a0, a1, and a2 input low voltage 0 0.2 x vcc v X96010
4 fn8214.1 october 25, 2005 notes: 1. the device goes into standby: 200 ns a fter any stop, except those that initia te a nonvolatile write cycle. it goes into standby t wc after a stop that initiates a nonvolatile write cycle. it also goes in to standby 9 clock cycles after any start that is not followed by the cor- rect slave address byte. 2. t wc is the time from a valid stop condition at the end of a wr ite sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. 3. for this range of v(vref) the full scale sink mode current at i1 and i2 follows v(vref) with a linearity error smaller than 1 %. 4. this parameter is periodically sampled and not 100% tested. 5. tco ref = [max v(v ref ) - min v(v ref )] x 10 6 /(1.21v x 140c) v ihcmos wp , a0, a1, and a2 input high voltage 0.8 x vcc vcc v vrefout output voltage at vref at 25c 1.205 1.21 1.215 v -20 a i(vref) 20 a rvref vref pin input resistance 20 40 k ? vrm bit = ?1?, 25c tcoref temperature coefficient of vref output voltage -100 +100 ppm/ c see note 4 and 5. vref range voltage range when vref is an input 1 1.3 v see note 3. i r current from pin r1 or r2 to vss 0 3200 a v por power-on reset threshold voltage 1.5 2.8 v vccramp vcc ramp rate 0.2 50 mv / s v adcok adc enable minimum voltage 2.6 2.8 v see figure 10. electrical characteristics (continued) (conditions are as follows, unless otherwise specified) all typical values are for 25c ambient temperature and 5v at pin vcc. maximum and minimu m specifications are over the recommended operating conditions. all voltages are referred to the voltage at pin vss. bit 3 in control register 0 is ?1?, while all other bits in control registers are ?0?. 255 ? , 0.1%, resistor connected between r1 and vss, and another between r2 and vss. 400khz ttl input at sc l. sda pulled to vcc through an external 2k ? resistor. 2-wire interface in ?standby? (see notes 1 and 2 on page 5). wp , a0, a1, and a2 floating. vref pin unloaded. symbol parameter min typ max unit test conditions / notes X96010
5 fn8214.1 october 25, 2005 d/a converter characteristics (see pg. 4 for standard conditions) notes: 1. dac input byte = ffh, source or sink mode. 2. lsb is defined as divided by the resistance between r1 or r2 to vss. 3. offset dac : the offset of a dac is defined as t he deviation between the measured and ideal out put, when the dac input is 01h. it is expressed in lsb. fserror dac : the full scale error of a dac is defi ned as the deviation between the measured and ideal output, when the input is ffh. it is expressed in lsb. the offset dac is subtracted from the measured value before calculating fserror dac . dnl dac : the differential non-linearity of a dac is defined as th e deviation between the measured and ideal incremental change in the output of the dac, when the input changes by one code step. it is expressed in lsb. the meas ured values are adjusted for of fset and full scale error before calculating dnl dac . inl dac : the integral non-linearity of a dac is defined as the deviati on between the measured and ideal transfer curves, after adjust- ing the measured transfer curve for offset and full scale error. it is expressed in lsb. 4. these parameters are periodically sampled and not 100% tested. 5. v(i1) and v(i2) are v cc - 1.2v in source mode and 1.2v in sink mode. in this range the current at i1 or i2 varies <1%. 6. the maximum current, sink or source, can be set with an external resistor to 3.2 ma with a minimum v cc = 4.5v. the compliance volt- age changes to 2.5v from the sourcing rail, and the current variation is <1%. symbol parameter min typ max unit test conditions / notes ifs i1 or i2 full scale current 1.56 1.58 1.6 ma see note 1, 5, r = 510 ? 3.2 ma see note 1, 4, 6, r = 255 ? offset dac i1 or i2 d/a converter offset error 1 1 lsb see notes 2 and 3. fserror dac i1 or i2 d/a converter full scale error -2 2 lsb dnl dac i1 or i2 d/a converter differential nonlinearity -0.5 0.5 lsb inl dac i1 or i2 d/a converter integral nonlin- earity with respect to a straight line through 0 and the full scale value -1 1 lsb v isink i1 or i2 sink voltage compliance 1.2 vcc v see note 5 2.5 vcc v see note 4, 6 v isource i1 or i2 source voltage compliance 0 vcc-1.2 v see note 5 0 vcc-2.5 v see note 4, 6 i over i1 or i2 overshoot on d/a converter data byte transition 0 a dac input byte changing from 00h to ffh and vice versa, v(i1) and v(i2) are vcc - 1.2v in source mode and 1.2v in sink mode. see note 4. i under i1 or i2 undershoot on d/a converter data byte transition 0 a t rdac i1 or i2 rise time on d/a converter data byte transition; 10% to 90% 530 s tco iout temperataure coefficient of output current due to internal parameters -100 +100 ppm/ c see figure 7. vrmbit = ?0? 2 3 v(vref) 255 x [] X96010
6 fn8214.1 october 25, 2005 a/d converter characteristics (see pg. 4 for standard conditions) notes: 1. ?lsb? is defined as v(vref)/255, ?full scale? is defined as v(vref). 2. offset adc : for an ideal converter, the first transition of its tr ansfer curve occurs at above zero. offset error is the amount of deviation between the measured fi rst transition point and the ideal point. fserror adc : for an ideal converter, the last transition of its tr ansfer curve occurs at . full scale error is the amount of deviation between the measured last transition point and the ideal point, after subtracting the offset from the measured curve. dnl adc : dnl is defined as the difference between the ideal and the measured code transitions for successive a/d code outputs expressed in lsbs. the measured transfer curve is adjusted for offset and fullscale errors before calculating dnl. inl adc : the deviation of the measured transfer function of an a/d conver ter from the ideal transfer function. the inl error is also defined as the sum of the dnl errors starting from code 00h to the code where the inl measuremen t is desired. the measured tran s- fer curve is adjusted for offset and fullscale errors before calculating inl. 3. these parameters are periodically sampled and not 100% tested. symbol parameter min typ max unit test conditions / notes adctime a/d converter conversion time 9 ms proportional to a/d converter input voltage. this value is maximum at full scale input of a/d converter. adcfiltoff = ?1? rin adc vsense pin input resistance 100 k ? vsense as an input, adcin bit = ?1? cin adc vsense pin input capacitance 1 7 pf vsense as an input, adcin bit = ?1?, frequency = 1 mhz see note 3. vin adc vsense input signal range 0 v(vref) v this is the a/d converter dynamic range. adcin bit = ?1? the adc is monotonic offset adc a/d converter offset error 1 lsb see notes 1 and 2 fserror adc a/d converter full scale error 1 lsb dnl adc a/d converter differential nonlinearity 0.5 lsb inl adc a/d converter integral nonlinearity 1 lsb 0.5 x v(vref) 255 [] 254.5 x v(vref) 255 [] X96010
7 fn8214.1 october 25, 2005 2-wire interface a.c. characteristics 2-wire interface test conditions nonvolatile write cycle timing notes: 1. cb = total capacitance of one bus line (sda or scl) in pf. 2. t wc is the time from a valid stop condition at the end of a wr ite sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. 3. the minimum frequency requirement applie s between a start and a stop condition. 4. these parameters are periodically sampled and not 100% tested. symbol parameter min typ max unit s test conditions / notes f scl scl clock frequency 1 (3) 400 khz see ?2-wire interface test conditions? (below), see figure 1, figure 2 and figure 3. t in (4) pulse width suppression time at inputs 50 ns t aa (4) scl low to sda data out valid 900 ns t buf (4) time the bus free before start of new transmission 1300 ns t low clock low time 1.3 1200 (3) s t high clock high time 0.6 1200 (3) s t su:sta start condition setup time 600 ns t hd:sta start condition hold time 600 ns t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 600 ns t dh data output hold time 50 ns t r (4) sda and scl rise time 20 +0.1cb (1) 300 ns t f (4) sda and scl fall time 20 +0.1cb (1) 300 ns t su:wp (4) wp setup time 600 ns t hd:wp (4) wp hold time 600 ns cb (4) capacitive load for each bus line 400 pf input pulse levels 10 % to 90 % of vcc input rise and fall times, between 10% and 90% 10 ns input and output timing threshold level 1.4v external load at pin sda 2.3k ? to vcc and 100 pf to vss symbol parameter min typ max units test conditions / notes t wc (2) nonvolatile write cycle time 5 10 ms see figure 3 X96010
8 fn8214.1 october 25, 2005 timing diagrams figure 1. bus timing figure 2. wp pin timing figure 3. non-volatile write cycle timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r t hd:wp scl sda in wp t su:wp clk 1 start stop scl sda t wc 8th bit of last byte ack stop condition start condition X96010
9 fn8214.1 october 25, 2005 intersil sensor conditioner product family fso = full scale output, ext = external, int = internal device description the X96010 contains two independent programmable current generators in one package. the combination of the X96010 func tionality and inte rsil?s qfn package lowers system cost, increa ses reliability, and reduces board space requirements. two on-chip programmable current generators may be independently programmed to either sink or source current. the maximum current generated is deter- mined by using an externally connected programming resistor. both current generators have a maximum output of 3.2 ma, and ma y be controlled to an abso- lute resolution of 0.39% (256 steps / 8 bit). both current generators may be driven using an exter- nal sensor or control regi sters. the external sensor output drives a 8-bit a/d converter. the six msbs of the adc output select one of 64 bytes from each non- volatile look-up table (lut). the contents of the selected lut row (8-bit wide) drives the input of an 8-bit d/a converter, which gener- ates the output current. all control and setup parameters of the X96010, including the look-up tables, are programmable via the 2-wire serial port. device title features / functions internal temperature sensor external sensor input internal voltage reference vref input / ouput general purpose eeprom look up table organi- zation # of dacs fso current dac setting resistors X96010 sensor conditioner with dual look-up table memory and dacs no yes yes yes no dual bank dual ext x96011 temperature sensor with look-up table memory and dac yes no yes no no single bank single int x96012 universal sensor conditioner with dual look-up table memory and dacs yes yes yes yes yes dual bank dual ext / int X96010
10 fn8214.1 october 25, 2005 principles of operation control and status registers the control and status registers provide the user with a mechanism for changing and reading the value of various parameters of the X96010. the X96010 contains seven control, one status, and several reserved registers, each being one byte wide (see figure 4). the control registers 0 through 6 are located at memory addresses 80h through 86h respectively. the status register is at memory address 87h, and the reserved registers at memory address 88h through 8fh. all bits in control register 6 always power-up to the logic state ?0?. all bits in control registers 0 through 5 power- up to the logic state value kept in their corresponding nonvolatile memory cells. t he nonvolatile bits of a reg- ister retain their stored values even when the X96010 is powered down, then powered back up. the nonvolatile bits in control 0 through control 5 registers are all pre- programmed to the logic state ?0? at the factory, except the cases that indicate ?1? in figure 4. bits indicated as ?reserved? are ignored when read, and must be written as ?0?, if any write operation is performed to their registers. a detailed description of the function of each of the control and status register bits follows: control register 0 this register is accessed by performing a read or write operation to address 80h of memory. vrm: v oltage r eference pin m ode (n on - volatile ) the vrm bit configures the voltage reference pin (vref) as either an input or an output. when the vrm bit is set to ?0? (default), the voltage at pin vref is an output from the X96010?s internal voltage reference. when the vrm bit is set to ?1?, the voltage reference for the vref pin is external. see figure 5. adc filt o ff : adc f iltering c ontrol (n on - volatile ) when this bit is?1?, the status register at 87h is updated after every conversion of the adc. when this bit is ?0? (default), the stat us register is updated after four consecutive conversions with the same result, on the 6 msbs. nv1234: c ontrol registers 1, 2, 3, and 4 vola - tility mode selection bit (n on - volatile ) when the nv1234 bit is set to ?0? (default), bytes writ- ten to control registers 1, 2, 3, and 4 are stored in vol- atile cells, and their content is lost when the X96010 is powered down. when the nv1234 bit is set to ?1?, bytes written to control regi sters 1, 2, 3, and 4 are stored in both vo latile and nonvolatile cells, and their value doesn?t change when the X96010 is powered down and powered back up. see ?writing to control registers? on page 23. i1ds: c urrent g enerator 1 d irection s elect b it (n on - volatile ) the i1ds bit sets the polarity of current generator 1, dac1. when this bit is set to ?0? (default), the current generator 1 of the X96010 is configured as a current source. current generator 1 is configured as a cur- rent sink when the i1ds bit is set to ?1?. see figure 7. X96010
11 fn8214.1 october 25, 2005 figure 4. control and status register format byte msb lsb 80h register control 0 00 i1ds nv1234 i2ds adcfiltoff 1 vrm non-volatile 81h control 1 volatile or reserved reserved l1da5 l1da4 l1da3 l1da2 l1da1 l1da0 82h control 2 volatile or reserved reserved l2da5 l2da4 l2da3 l2da2 l2da1 l2da0 83h control 3 volatile or d1da7 d1da6 d1da5 d1da4 d1da3 d1da2 d1da1 d1da0 non-volatile non-volatile non-volatile 84h control 4 volatile or d2da7 d2da6 d2da5 d2da4 d2da3 d2da2 d2da1 d2da0 non-volatile 85h control 5 non-volatile d2das l2das d1das l1das 0 0 0 0 86h control 6 volatile wel reserved reserved reserved reserved reserved reserved reserved 87h status volatile ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 7 6 5 4 3 21 0 name address registers in byte addresses 88h through 8fh are reserved. direct access to lut1 direct access to lut2 direct access to dac1 direct access to dac2 adc output i1 and i2 direction 0: source 1: sink control 1, 2, 3, 4 volatility 0: volatile 1: non- volatile voltage reference mode 0: internal 1: external direct access to dac2 0: disabled 1: enabled direct direct direct access to lut2 0: disabled 1: enabled access to dac1 access to lut1 0: disabled 0: disabled 1: enabled 1: enabled write enable latch 0: write disabled 1: write enabled adc 0: on 1: off filtering register bits shown as 0 or 1 should al ways use those values for proper operation. X96010
12 fn8214.1 october 25, 2005 i2ds: c urrent g enerator 2 d irection s elect b it (n on - volatile ) the i2ds bit sets the polarity of current generator 2, dac2. when this bit is set to ?0? (default), the current generator 2 of the X96010 is configured as a current source. current generator 2 is configured as a cur- rent sink when the i2ds bit is set to ?1?. see figure 7. control register 1 this register is accessed by performing a read or write operation to address 81h of memory. this byte?s volatility is determined by bit nv1234 in control register 0. l1da5 - l1da0: lut1 d irect a ccess b its when bit l1das (bit 4 in control register 5) is set to ?1?, lut1 is addressed by these six bits, and it is not addressed by the output of the on-chip a/d converter. when bit l1das is set to ?0?, these six bits are ignored by the X96010. see figure 9. a value between 00h (00 10 ) and 3fh (63 10 ) may be writ- ten to these register bits, to select the corresponding row in lut1. the written value is added to the base address of lut1 (90h). control register 2 this register is accessed by performing a read or write operation to address 82h of memory. this byte?s vola- tility is determined by bit nv 1234 in control register 0. l2da5 - l2da0: lut2 d irect a ccess b its when bit l2das (bit 6 in control register 5) is set to ?1?, lut2 is addressed by these six bits, and it is not addressed by the output of the on-chip a/d converter. when bit l2das is set to ?0?, these six bits are ignored by the X96010. see figure 9. a value between 00h (00 10 ) and 3fh (63 10 ) may be writ- ten to these register bits, to select the corresponding row in lut2. the written value is added to the base address of lut2 (d0h). control register 3 this register is accessed by performing a read or write operation to address 83h of memory. this byte?s volatility is determined by bit nv1234 in control register 0. d1da7 - d1da0: d/a 1 d irect a ccess b its when bit d1das (bit 5 in control register 5) is set to ?1?, the input to the d/a converter 1 is the content of bits d1da7 - d1da0, and it is not a row of lut1. when bit d1das is set to ?0? (default) these eight bits are ignored by the X96010. see figure 8. control register 4 this register is accessed by performing a read or write operation to address 84h of memory. this byte?s volatil- ity is determined by bit nv1234 in control register 0. d2da7 - d2da0: d/a 2 d irect a ccess b its when bit d2das (bit 7 in control register 5) is set to ?1?, the input to the d/a converter 1 is the content of bits d2da7 - d2da0, and it is not a row of lut2. when bit d2das is set to ?0? (default) these eight bits are ignored by the X96010. (see figure 8). control register 5 this register is accessed by performing a read or write operation to address 85h of memory. l1das: lut1 d irect a ccess s elect b it (n on - volatile ) when bit l1das is set to ?0? (default), lut1 is addressed by the output of the on-chip a/d converter. when bit l1das is set to ?1?, lut1 is addressed by bits l1da5 - l1da0. d1das: d/a 1 d irect a ccess s elect b it (n on - volatile ) when bit d1das is set to ?0? (default), the input to the d/a converter 1 is a row of lut1. when bit d1das is set to ?1?, that input is the content of the control register 3. X96010
13 fn8214.1 october 25, 2005 l2das: lut2 d irect a ccess s elect b it (n on - volatile ) when bit l2das is set to ?0? (default), lut2 is addressed by the output of the on-chip a/d converter. when bit l2das is set to ?1?, lut2 is addressed by bits l2da5 - l2da0. d2das: d/a 2 d irect a ccess s elect b it (n on - volatile ) when bit d2das is set to ?0? (default), the input to the d/a converter 2 is a row of lut2. when bit d2das is set to ?1?, that input is the content of the control register 4. control register 6 this register is accessed by performing a read or write operation to address 86h of memory. wel: w rite e nable l atch (v olatile ) the wel bit controls the wr ite enable status of the entire X96010 device. this bit must be set to ?1? before any other write operation (vol atile or nonvolatile). oth- erwise, any proceeding write operation to memory is aborted and no ack is issued after a data byte. the wel bit is a volatile latch that powers up in the ?0? state (disabled). the wel bit is enabled by writing 10000000 2 to control register 6. once enabled, the wel bit remains set to ?1? until the X96010 is powered down, and then up again, or until it is reset to ?0? by writing 00000000 2 to control register 6. a write operation that modifies the value of the wel bit will not cause a change in other bits of control register 6. status register - adc output this register is accessed by performing a read opera- tion to address 87h of memory. ad7 - ad0: a/d c onverter o utput b its (r ead only ) these eight bits are the binary output of the on-chip a/d converter. the output is 00000000 2 for minimum input and 11111111 2 for full scale input. the six msbs select a row of the luts. X96010
14 fn8214.1 october 25, 2005 voltage reference the voltage reference to the a/d and d/a converters on the X96010, may be driven from the on-chip volt- age reference, or from an external source via the vref pin. bit vrm in control register 0 selects between the two options (see figure 5). the default value of vrm is ?0?, which selects the internal reference. when the internal reference is selected, it?s output voltage is also an output at pin vref with a nominal value of 1.21 v. if an external voltage reference is preferred, the vrm bit of the con- trol register 0 must be set to ?1?. figure 5. voltage reference structure a/d converter the X96010 contains a genera l purpose, on-chip, 8-bit analog to digital (a/d) converter whose output is avail- able at the status register as bits ad[7:0]. by default these output bits are used to select a row in the look- up tables associated with the X96010?s current gen- erators. when bit adcfiltof f is ?0? (default), bits ad[7:0] are updated each time the adc performs four consecutive conversions with the same exact result at the 6 msbs. when bit adcfiltoff is ?1?, these bits are updated after every adc conversion. a block diagram of the a/d converter is shown in fig- ure 6. the voltage reference input (see ?voltage reference? for details), sets the maximum ampli- tude of the ramp generator output. the a/d converter input signal (see ?a/d converter input select? below for details) is compared to the ramp generator output. the control and encode logic produces a binary encoded output, with a minimum value of 00h (0 10 ), and a full scale output value of ffh (255 10 ). the a/d converter input voltage range (vin adc ) is from 0 v to v(vref). vrm: bit 2 in control register 0. vref pin on-chip a/d converter and voltage reference d/a converters reference figure 6. a/d converter block diagram ramp generator vsense pin from vref clock control and encode logic conversion reset a/d converter output (to luts and status register) 8 comparator X96010
15 fn8214.1 october 25, 2005 a/d converter range from figure 6 we can see that the operating range of the a/d converter input depends on the voltage reference. the table below summarizes the voltage range restrictions on the vsense and vref pins in different configurations : vsense and vref ranges look-up tables the X96010 memory array contains two 64-byte look- up tables. one is associated to pin i1?s output current generator and the other to pin i2?s output current gen- erator, through their corresponding d/a converters. the output of each look-up table is the byte contained in the selected row. by default these bytes are the inputs to the d/a converters driving pins i1 and i2. the byte address of the selected row is obtained by adding the look-up table base address (90h for lut1, and d0h for lut2) and the appropriate row selection bits. see figure 8. by default the look-up table selection bits are the 6 msbs of the a/d converter output. alternatively, the a/d converter can be bypassed and the six row selection bits are the six lsbs of control registers 1 and 2, for the lut1 and lut2 respectively. the selection between these opti ons is illustrated in fig- ure 9, and described in ?i2ds: current g enerator 2 direction select bit (non-volatile)? on page 12, and ?control register 2? on page 12. current generator block the current generator pins i1 and i2 are outputs of two independent current mode d/a converters. d/a converter operation the block diagram for each of the d/a converters is shown in figure 7. the input byte of the d/a converter selects a voltage on the non-inverting input of an operational amplifier. the output of the amplifier drives the gate of a fet, whose source is connected to ground via resistor r1 or r2. this node is also fe d back to the inverting input of the amplifier. the drain of the fet is connected to the output current pin (i1 or i2) via a ?polarity select? circuit block. vref a/d converter input ranges internal vsense pin 0 v(vsense) v(vref) external vsense pin 0 v(vref) 1.3 v 0 v(vsense) v(vref) all voltages referred to vss. X96010
16 fn8214.1 october 25, 2005 figure 7. d/a converter block diagram + - i1 or i2 pin r1 or r2 pin i1ds or i2ds: bits vref external resistor select circuit polarity vcc voltage 6 or 7 in control register 0. divider dac1 or dac2 input byte vss figure 8. look-up table (lut) operation dac 2 8 d0h d0h 10fh 8 lut2 6 lut2 row out d1 d0 select d2das: bit 7 of d2da[7:0] : control register 4 selection bits a d d e r 8 8 input byte control register 5 dac 1 8 90h 90h cfh 8 lut1 6 lut1 row out d1 d0 select d1das: bit 5 of d1da[7:0] : control register 3 selection bits a d d e r 8 8 input byte control register 5 ? ? X96010
17 fn8214.1 october 25, 2005 by examining the block diagram in figure 7, we see that the maximum current through pin i1 is set by fixing values for v(vref) and r1. the output current can then be varied by changing the data byte at the d/a converter input. in general, the magnitude of the current at the d/a converter output pins (i1, i2) may be calculated by: ix = (v(vref) / (384 ? rx)) ? n where x = 1,2 and n is the decimal representation of the input byte to the corresponding d/a converter. the value for the resistor rx (x = 1,2) determines the full scale output current that the d/a converter may sink or source. the full scale output current has a maximum value of 3.2 ma, which is obtained using a resistance of 255 ? for rx. this resistance is con- nected externally to pin rx of the X96010. bits i1ds and i2ds in control register 0 select the direction of the currents through pins i1 and i2 inde- pendently (see ?i1ds: current generator 1 direction select bit (non-volatile)? on page 10 and ?control and status register format? on page 11). d/a converter output current response when the d/a converter input data byte changes by an arbitrary number of bits, the output current changes from an intial current level (i x ) to some final level (i x + ? i x ). the transition is monotonic and glitchless. d/a converter control the data byte inputs of the d/a converters can be con- trolled in three ways: ? 1) with the a/d converter and through the look-up tables (default), ? 2) bypassing the a/d converter and directly accessing the look-up tables, ? 3) bypassing both the a/d converter and look-up tables, and directly setting the d/a converter input byte. the options are summarized in the following tables: d1 d0 select adc ad[7:0] lut1 row lut2 row out d1 d0 select voltage voltage input selection bits selection bits reference out l2da[5:0]: control register 2 l1da[5:0]: control register 1 l2das: bit 6 in control register 5 l1das: bit 4 in control register 5 6 6 status register figure 9. look-up table addressing 8 X96010
18 fn8214.1 october 25, 2005 d/a converter 1 access summary d/a converter 2 access summary the a/d converter is shared between the two current generators but the look-up tables, d/a converters, control bits, and selection bits can be set completely independently. bits d1das and d2das are used to bypass the a/d converter and look-up tables, allowing direct access to the inputs of the d/a conver ters with the bytes in con- trol registers 3 and 4 respectively. see figure 8, and the descriptions of the control bits. bits i1ds and i2ds in control register 0 select the direction of the currents through pins i1 and i2 inde- pendently see figure 7, and the descriptions of the control bits. power-on reset when power is applied to the vcc pin of the X96010, the device undergoes a strict sequence of events before the current outputs of the d/a converters are enabled. when the voltage at vcc becomes larger than the power-on reset threshold voltage (v por ), the device recalls all control bits from non-volatile memory into volatile registers. next, the analog circuits are pow- ered up. when the voltage at vcc becomes larger than a second voltage threshold (v adcok ), the adc is enabled. in the default case, after the adc performs four consecutive conversions with the same exact result, the adc output is used to select a byte from each look-up table. those bytes become the input of the dacs. during all the previous sequence the input of both dacs are 00h. if bi t adcfiltoff is ?1?, only one adc conversion is necessa ry. bits d1das, d2das, l1das, and l2das, also modify the way the two dacs are accessed the first time after power- uppower-up, as described in ?control register 5? on page 12. the X96010 is a hot pluggable device. voltage dis- trubances on the vcc pin are handled by the power-on reset circuit, allowing proper operation during hot plug- in applications. serial interface serial interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. the X96010 operates as a slave in all applications. l1das d1das control source 0 0 a/d converter through lut1 (default) 1 0 bits l1da5 - l1da0 through lut1 x 1 bits d1da7 - d1da0 ?x? = don?t care condition (may be either ?1? or ?0?) l2das d2das control source 0 0 a/d converter through lut2 (default) 1 0 bits l2da5 - l2da0 through lut2 x 1 bits d2da7 - d2da0 ?x? = don?t care condition (may be either ?1? or ?0?) X96010
19 fn8214.1 october 25, 2005 serial clock and data data states on the sda line can change only while scl is low. sda state changes while scl is high are reserved for indicating start and stop condi- tions. see figure 12. on power-up of the X96010, the sda pin is in the input mode. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda while scl is high. the device contin uously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met. see figure 11. serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see figure 11. serial acknowledge an ack (acknowledge), is a software convention used to indicate a successful da ta transfer. th e transmitting device, either master or slave, releases the bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data. see figure 13. the device responds with an ack after recognition of a start condition followed by a valid slave address byte. a valid slave address byte must contain the device type identifier 1010, and the device address bits matching the logic state of pins a2, a1, and a0. see figure 15. if a write operation is selected, the device responds with an ack after the receipt of each subsequent eight-bit word. in the read mode, the device transmits eight bits of data, releases the sda line, and then monitors the line for an ack. the device cont inues transmitting data if an ack is detected. the device terminates further data transmissions if an ack is not detected. the master must then issue a stop condition to place the device into a known state. the X96010 acknowledges all incoming data and address bytes except: 1) the ?slave address byte? when the ?device identifier ? or ?device address? are wrong; 2) all ?data bytes? when the ?wel? bit is ?0?, with the exception of a ?data byte? addresses to loca- tion 86h; 3) ?data bytes? following a ?data byte? addressed to locations 80h, 85h, or 86h. figure 10. d/a converter power-on reset response i x i x x 10% adc time current time time vcc v adcok 0v voltage X96010
20 fn8214.1 october 25, 2005 figure 11. valid start and stop conditions figure 12. valid data changes on the sda bus figure 13. acknowledge response from receiver scl sda start stop scl sda data stable data change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master X96010
21 fn8214.1 october 25, 2005 X96010 memory map the X96010 contains a 144 byte array of mixed vola- tile and nonvolatile memory. this array is split up into three distinct parts, namely: (refer to figure 14.) ? look-up table 1 (lut1) ? look-up table 2 (lut2) ? control and status registers figure 14. X96010 memory map the control and status registers of the X96010 are used in the test and setup of the device in a system. these registers are realized as a combination of both volatile and nonvolatile memory. these registers reside in the memory locations 80h through 8fh. the reserved bits within registers 80h through 86h, must be written as ?0? if writ ing to them, and should be ignored when reading. register bits shown as 0 or 1, in figure 4, must be written with the indicated value if writing to them. the reserved registers, from 88h through 8fh, must not be written, and their content should be ignored. both look-up tables lut1 and lut2 are realized as nonvolatile eeprom, and extend from memory loca- tions 90h - cfh and d0h - 10fh respectively. these look-up tables are dedicated to storing data solely for the purpose of setting the outputs of current genera- tors i1 and i2 respectively. all bits in both look-up tables are preprogrammed to ?0? at the factory. addressing protocol overview all serial interface operations must begin with a start, followed by a slave address byte. the slave address selects the X96010, and specifies if a read or write operation is to be performed. it should be noted that the write enable latch (wel) bit must first be set in order to perform a write opera- tion to any other bit. (see ?wel: write enable latch (volatile)? on page 13.) al so, all communication to the X96010 over the 2-wire serial bus is conducted by sending the msb of each byte of data first. the memory is physically realized as one contiguous array, organized as 9 pages of 16 bytes each. the X96010 2-wire protocol provides one address byte, therefore the next few sections explain how to access the different areas for reading and writing. figure 15. slave address (sa) format look-up table 2 (lut2) address size 64 bytes 64 bytes 16 bytes 10fh 80h 8fh 90h cfh d0h ffh look-up table 1 (lut1) control & status registers sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read or sa4 slave address bit(s) description sa7 - sa4 device type identifier sa3 - sa1 device address sa0 read or write operation select r/w 1010 address device as0 as1 as2 write X96010
22 fn8214.1 october 25, 2005 slave address byte following a start condition, the master must output a slave address byte (refer to figure 15.). this byte includes three parts: ? the four msbs (sa7 - sa4) are the device type identifier, which must always be set to 1010 in order to select the X96010. ? the next three bits (sa3 - sa1) are the device address bits (as2 - as0). to access any part of the X96010?s memory, the val ue of bits as2, as1, and as0 must correspond to the logic levels at pins a2, a1, and a0 respectively. ? the lsb (sa0 ) is the r/w bit. this bit defines the operation to be performed on the device being addressed. when the r/w bit is ?1?, then a read operation is selected. a ?0? selects a write operation (refer to figure 15.) nonvolatile write acknowledge polling after a nonvolatile write command sequence is cor- rectly issued (including the final stop condition), the X96010 initiates an internal high voltage write cycle. this cycle typically requires 5 ms. during this time, any read or write command is ignored by the X96010. write acknowledge polling is used to deter- mine whether a high volta ge write cycle is completed. during acknowledge polling, the master first issues a start condition followed by a slave address byte. the slave address byte cont ains the X96010?s device type identifier and device address. the lsb of the slave address (r/w ) can be set to either 1 or 0 in this case. if the device is busy within the high voltage cycle, then no ack is returned. if the high voltage cycle is completed, an ack is returned and the master can then proceed with a new read or write operation. (refer to figure 16.). byte write operation in order to perform a byte write operation to the mem- ory array, the write enable latch (wel) bit of the con- trol 6 register must first be set to ?1?. (see ?wel: write enable latch (volatile)? on page 13.) for any byte write operation, the X96010 requires the slave address byte, an address byte, and a data byte (see figure 17). after each of them, the X96010 responds with an ack. the master then terminates the transfer by generating a stop condition. at this time, if all data bits are volatile, the X96010 is ready for the next read or write operation. if some bits are non- volatile, the X96010 begins the internal write cycle to the nonvolatile memory. during the internal nonvolatile write cycle, the X96010 does not respond to any requests from the master. the sda output is at high impedance. a byte write operation can access bytes at locations 80h through feh directly, when setting the address byte to 80h through feh respectively. setting the address byte to ffh acce sses the byte at location 100h. the other sixteen bytes, at locations ffh and 101h through 10fh can only be accessed using page write operations. the byte at location ffh can only be written using a ?page write? operation. writing to control bytes which are located at byte addresses 80h through 8fh is a special case described in the section ?writing to control registers? . ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes no continue normal read or write command sequence proceed yes complete. continue command sequence. high voltage issue stop figure 16. acknowledge polling sequence X96010
23 fn8214.1 october 25, 2005 page write operation the 144-byte memory array is physically realized as one contiguous array, organized as 9 pages of 16 bytes each. ?page write? operations can be performed to any of the lut pages. in order to perform a page write operation the write enable latch (wel) bit in control register 6 must first be set (see ?wel: write enable latch (volatile)? on page 13.) a page write operation is in itiated in th e same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 16 bytes (see figure 18). after the receipt of each byte, the X96010 responds with an ack, and the internal byte address counter is incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to the first byte of the same page. for example, if the master writes 12 bytes to a 16-byte page starting at location 11 (decimal), the first 5 bytes are written to locations 11 through 15, while the last 7 bytes are written to locations 0 through 6 within that page. afterwards, the address counter would point to location 7. if the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time (see figure 19). the master terminates the loading of data bytes by issuing a stop condition, which initiates the nonvola- tile write cycle. as with th e byte write operation, all inputs are disabled until completion of the internal write cycle. a page write operation cannot be performed on the page at locations 80h th rough 8fh. next section describes the special cases within that page. a page write operation starting with byte address ffh, accesses the page between locations 100h and 10fh. the first data byte of such operation is written to location 100h. writing to control registers the bytes at location 80h, 85h and 86h are written using byte write operations. they cannot be written using a page write operation. control bytes 1 through 4, at locations 81h through 84h respectively, are written during a single operation (see figure 20). the sequence must be: a start, followed by a slave address byte, with the r/w bit equal to ?0?, followed by 81h as the addr ess byte, and then followed by exactly four data bytes, and a stop condition. the first data byte is written to location 81h, the second to 82h, the third to 83h, and the last one to 84h. s t a r t s t o p slave address address byte data byte a c k signals from the master signals from the slave a c k 1 0 1 00 a c k write signal at sda figure 17. byte write sequence 2 < n < 16 signals from the master signals from the slave signal at sda s t a r t slave address address byte a c k a c k 1 0 1 00 data byte (1) s t o p a c k a c k data byte (n) write figure 18. page write operation X96010
24 fn8214.1 october 25, 2005 the four registers control 1 through 4, have a nonvol- atile and a volatile cell for each bit. at power-up, the content of the nonvolatile cells is automatically recalled and written to the volatile cells. the content of the volatile cells controls the X96010?s functionality. if bit nv1234 in the control 0 register is set to ?1?, a write operation to these registers writes to both the volatile and nonvolatile cells. if bit nv1234 in the con- trol 0 register is set to ?0?, a write operation to these registers only writes to the volatile cells. in both cases the newly written values effectively control the X96010, but in the second case, those values are lost when the part is powered down. if bit nv1234 is set to ?0?, a byte write operation to control registers 0 or 5 causes the value in the nonvol- atile cells of control registers 1 through 4 to be recalled into their correspondi ng volatile cells, as dur- ing power-up. this doesn?t happen when the wp pin is low, because write protection is enabled. it is gener- ally recommended to configure control registers 0 and 5 before writing to control registers 1 through 4. when reading any of the contro l registers 1, 2, 3, or 4, the data bytes are always the content of the corre- sponding nonvolatile cells, ev en if bit nv1234 is "0" (see ?control and stat us register format?). read operation a read operation consist of a three byte instruction followed by one or more data bytes (see figure 21). the master initiates the op eration issuing the following sequence: a start, the slave address byte with the r/w bit set to ?0?, an address byte, a second start, and a second slave address byte with the r/w bit set to ?1?. after each of the three bytes, the X96010 responds with an ack. then the X96010 transmits data bytes as long as the master responds with an ack during the scl cycle following the eigth bit of each byte. the master terminates the read operation (issuing a stop condition) following the last bit of the last data byte (see figure 21). 5 bytes 7 bytes address = 6 5 bytes address pointer address = 15 address = 11 ends up here address = 7 address = 0 figure 19. example: writing 12 bytes to a 16-byte page starting at location 11. signals from the master signals from the slave signal at sda s t a r t slave address address byte = 81h a c k a c k 1 0 1 00 data byte for control 1 s t o p a c k a c k data byte for control 4 write 1 1 0 00 0 0 0 four data bytes figure 20. writing to control registers 1, 2, 3, and 4 X96010
25 fn8214.1 october 25, 2005 the data bytes are from the memory location indicated by an internal pointer. this pointer initial value is deter- mined by the address byte in the read operation instruc- tion, and increments by one during transmission of each data byte. after reaching the memory location 10fh, a stop should be issued. if the read operation continues, the output bytes are unpredictable. if the address is set between 00h and 7fh, the output bytes are unpredictable. a read operation internal pointer can start at any memory location from 80h through feh, when the address byte is 80h through feh respectively. but it starts at location 100h if the address byte is ffh. when reading any of the control registers 1, 2, 3, or 4, the data bytes are always the content of the corre- sponding nonvolatile cells, even if bit nv1234 is "0" (see ?control and status register format?). data protection there are three levels of data protection designed into the X96010: 1- any write to the device first requires setting of the wel bit in control 6 register; 2- the write protection pin disables any writing to the X96010; 3- the proper clock count, data bit sequence, and stop condition is required in order to start a nonvol- atile write cycle, otherwise the X96010 ignores the write operation. wp : write protection pin when the write protection (wp ) pin is active (low), any write operations to the X96010 is disabled, except the writing of the wel bit. signals from the master signals from the slave signal at sda s t a r t slave address with r/w = 0 address byte a c k a c k 1 0 1 00 s t o p a c k 1 1 1 00 slave address with r/w = 1 a c k s t a r t last read data byte first read data byte a c k figure 21. read sequence X96010
26 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8214.1 october 25, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package code v14 see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) X96010

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